Projects

Talking Ben FPGA

A full hardware recreation of the classic Talking Ben game on FPGA, featuring voice detection, DDR3 video/audio storage, and real-time VGA output.

Hardware Architecture

Scroll to explore the FPGA components

Urbana FPGA Board
DDR3 Memory 128MB for frames & audio
BRAM Buffer Ping-pong frame buffer
VGA Controller HDMI output timing
Audio PWM WAV playback module
PDM Microphone Voice detection input
UART PC data transfer
Animation FSM Game state controller
LFSR Random response generator
Scroll to explore

System Block Diagram

Click on any component to view details

Select a component

                        

                    

                

            


            
            

                
System Components

                

                    

                        
Video Pipeline

                        
DDR3 storage with ping-pong BRAM buffer for glitch-free VGA output at 60Hz

                    

                    

                        
Audio Pipeline

                        
WAV file playback through PWM with DDR3 arbiter for concurrent access

                    

                    

                        
Voice Detection

                        
PDM microphone with amplitude detection triggering random responses

                    

                    

                        
Animation FSM

                        
State machine controlling game flow with LFSR for random response selection

                    

                

            


            
            

                
Built With

                

                    SystemVerilog
                    Vivado
                    DDR3
                    VGA/HDMI
                    Python
                

            

        

        © Neil Rayu